The present invention relates to a digital-to-analog conversion circuit converting a digital amount into an analog amount and an image display apparatus displaying an image based on a digital image signal by using the digital-to-analog conversion circuit.
One of known image display apparatuses using a digital-to-analog conversion circuit is an image display apparatus of active matrix type using liquid crystal, the structure of which is schematically shown in FIG. 20. As shown in FIG. 20, the image display apparatus includes a pixel array PIXARY consisting of a plurality of pixels PIX arrayed in a matrix form, a scanning signal line driving circuit GD, a data signal line driving circuit SD, a plurality of scanning signal lines GL1-GLy extending along rows of the pixels PIX, and a plurality of data signal lines SL1-SLx extending along columns of the pixels PIX. The data signal line driving circuit SD samples a digital signal DAT, which is digital image data inputted thereto, in synchronization with timing signals such as a clock signal CKS and a start signal SPS generated by a control signal generator CTB. Then the circuit SD amplifies the sampled digital signal DAT as necessary, and outputs a data signal, which is analog image data, to each of the data signal lines SL1-SLx. The scanning signal line driving circuit GD selects the scanning signal lines GL1-GLy sequentially in synchronization with a timing signal such as a clock signal CKG generated by the control signal generator CTB to turn on and off switching elements provided in the respective pixels PIX. The data signal outputted to each of the data signal lines SL1-SLx is thereby written to the pixels PIX. A capacitor provided in each pixel PIX holds the written data signal.
Hitherto, the data signal line driving circuit SD and the scanning signal line driving circuit GD have generally been provided as external ICs separate from an insulation substrate on which the pixel array PIXARY is formed. In recent years, to reduce the assembling cost and improve reliability in assembling, a technique of forming all of the pixel array, the data signal line driving circuit, and scanning signal line monolithically on the insulation substrate has been reported.
Description will be made on the construction of the data signal line driving circuit of the image display apparatus of active matrix type. The data signal line driving circuit uses a digital-to-analog conversion circuit in which a reference voltage inputted from the outside is applied to a capacitor array through a switching circuit which switches according to whether the inputted digital signal (digital image data) has a high level or a low level, and a charge Q according to the applied voltage is held therein. For the sake of a brief description, suppose that an 8-bit signal is inputted to the data signal line driving circuit.
FIG. 21 shows a fundamental block of the data signal line driving circuit SD. As shown in FIG. 21, for one stage, i.e., for one data signal line SL, the data signal line driving circuit SD includes one scanning circuit SR, a switching circuit SWC performing the switching operation according to the level (high or low) of the input digital signal DAT1-DAT8 and the output from the scanning circuit SR, a capacitor array CAPARY having capacitors C1-C8 having different areas, namely, different capacitances set at the ratio of 20:21:22:23:24:25:26:27 in the order of bit position in the input digital signal from the least significant bit (LSB) to the most significant bit (MSB), and an output circuit BUF outputting a data signal to the corresponding data signal line SL, according to a charge amount held by each of the capacitors C1-C8 of the capacitor array CAPARY. The switching circuit SWC, the capacitor array CAPARY, and the output circuit BUF constitutes a digital-to-analog conversion circuit of charge distribution type.
The switching circuit SWC includes NAND circuits (non-conjunction circuits) NAND1-NAND8 to which an output signal of the scanning circuit SR is inputted through one input terminal thereof and the digital signals DAT1-DAT8 are inputted through the other input terminal thereof, and switches SW1-SW8 whose control input terminals are connected to output terminals of the NAND circuits NAND1-NAND8 respectively and whose output terminals are connected to one end of the capacitors C1-C8 respectively. A reference potential V1 for digital-to-analog conversion is connected to one input terminal of each of the switches SW1-SW8. A ground GND is connected to the other input terminal of each of the switches SW1-SW8.
The operation of the data signal line driving circuit SD will be described below.
When both the digital signal DAT1-DAT8 and the output signal of the scanning circuit SR have a high level, the output signal of the corresponding non-conjunction circuit NAND1-NAND8 has a low level. As a result, the associated switch SW1-SW8 is switched to the side of the reference potential V1. Consequently the reference potential V1 is applied to the associated capacitor C1-CB. On the other hand, when the output signal of a non-conjunction circuit NAND1-NAND8 has a high level, the associated switch SW1-SW8 is changed to the side of the ground GND. Consequently the ground GND is connected to the associated capacitor C1-C8.
Supposing that the total of capacitances of those capacitors C1-C8 that are connected to the digital-to-analog conversion reference potential V1 side is Con and that the total of capacitances of those capacitors C1-C8 that are connected to the ground GND side is Coff, a voltage Vout at an output end commonly connected to the capacitors C1-C8 is expressed as follows:Vout=V1×Con/(Con+Coff)
The output circuit BUF current-amplifies the voltage Vout in synchronization with a transfer signal TRFS and outputs a data signal having a voltage corresponding to the voltage Vout to the corresponding data signal line SL.
The digital-to-analog conversion circuit of charge distribution type for use in the data signal line driving circuit SD executes a digital-to-analog conversion by distributing the charge with the capacitors C1-C8. The capacitances of the capacitors C1-C8 are changed to be increased at the ratio corresponding to the area ratio of 20:21:22:23:24:25:26:27 in order of bit position of the input digital signal from the least significant bit to the most significant bit. Accordingly, the driving capacity or ability required for each analog switch SW1-SW8 is different according to an on-state and an off-state of the other analog switches SW1-SW8 of the switching circuit SWC connecting the one end of each of the capacitors C1-C8 to the reference potential V1 or the ground GND. Therefore, it is necessary to give each of the analog switches SW1-SW8 a driving capacity high enough to charge the capacitors C1-C8 within a predetermined digital-to-analog conversion period of time, considering a capacitor connection that provides the largest synthetic capacitance among all possible capacitor connections. Normally, the analog switches SW1-SW8 are constructed of transistors. The driving capacity β of the analog switch SW1-SW8 is expressed as follows:β=μ×(∈ox×W)/(Tox×L)where μ is the mobility of electrons (holes), ∈ox is the dielectric constant of a gate insulation film, Tox is the thickness of the gate insulation film, L is the length of the gate of the transistor, W is the width of the gate of the transistor. The parameters μ, ∈ox, Tox, and L are uniquely determined according to factors such as a manufacturing process condition, a withstand pressure determined according to the purpose of use of the transistor, and reliability. Accordingly, the driving capacity of the transistor is adjustable according to its gate width W.
In the digital-to-analog conversion circuit, as described above, the transistors constituting the analog switches SW1-SW8 are required to have driving capacity high enough to charge the capacitors C1-C8 within a predetermined digital-to-analog conversion period of time in consideration of such a capacitor connection as can provide the highest synthetic capacitance of all possible capacitor connections. Such driving capacity can be obtained by increasing the gate width W of the transistors. But maximum connection capacitances corresponding to the analog switches SW1-SW8 are much different from one another. There is a big difference between a maximum connection capacitance Cmax corresponding to the switch to be connected to the capacitor having the maximum capacitance and a maximum connection capacitance Cmin corresponding to the switch to be connected to the capacitor having the minimum capacitance.
In the digital-to-analog conversion circuit, all the analog switches SW1-SW8 have the same size. That is, even the analog switch W1 to be connected to the capacitor C1 having the minimum capacitance is given a gate width W equal to that of the analog switch W8 to be connected to the capacitor C8 having the maximum capacitance. It follows that the transistors constituting the analog switch have sizes larger than necessary. Thus the analog switches occupy a large area in the digital-to-analog conversion circuit. Accordingly, in the image display apparatus of active matrix type, the display driving circuit (data signal line driving circuit) which is disposed in the periphery of a display region has a large area. That is, the ratio of the area of the frame to the display region in the image display apparatus is large.
Further in recent years, portable information terminal equipment has come into wide use. Because liquid crystal display apparatuses are thin, there is a growing demand for them as displays for the portable information terminal equipment. The portable information terminal equipment is required to be compact. Therefore, for the image display apparatuses themselves, it is required to reduce the size of the display driving circuit without reducing a display region, namely, to reduce the frame size.